Semiconductor memory devices may be classified into read access memory (RAM) types, such as a dynamic RAM (DRAM) and a static RAM (SRAM), and read only memory (ROM) types. RAM has relatively fast data input/output performance and volatility that loses data as time passes while ROM has relatively slow data input/output performance and non-volatility that retains data once input. The ROM types include ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically erasable PROM (EEPROM). Among the ROM types, the demand for the EEPROM that is electrically programmable or erasable has been increasing.
A flash memory cell capable of simultaneous erasing in the same manner as the EEPROM has a stacked floating gate and control gate. Such flash memory cells are widely used in notebook computers, PDAs, computer basic input/output systems (BIOS), printers and the like.
In view of the circuit structure, flash memory cells may be classified into a NAND type and a NOR type. NAND flash memory cells include n-number of cell transistors serially connected, forming a unit string. Since the unit strings are connected in parallel between a bit line and a ground line, it becomes easier to achieve high integration. In NOR flash memory cells, since the cell transistors are connected in parallel between the bit line and the ground line, the operation speed is high.
The structure and the operation of a related NOR flash memory cell will now be explained with reference to FIG. 1 and FIG. 2. FIG. 1 is an equivalent circuit view of a flash memory cell array and FIG. 2 is a longitudinal sectional view of a unit cell shown in FIG. 1.
Referring to FIG. 1, the flash memory cell includes a plurality of word lines W/L and a plurality of bit lines B/L crossing each other, and a plurality of memory cells MC connected between the word lines and the bit lines. Source regions of the respective memory cells MC are connected to a common source line CSL.
The structure of the memory cell MC is illustrated in FIG. 2. A tunnel oxide layer 11 is formed between a floating gate 12 and a semiconductor substrate 10. An interlayer dielectric 13 having a high-k dielectric oxide-nitride-oxide (ONO) structure is formed between the floating gate 12 and a control gate 14 supplied to the word line W/L.
Additionally, source/drain regions 15 and 16 are formed as self-aligned on a stacked gate. The flash memory cell stores and deletes data as electric charges are injected and discharged by channel hot carrier injection or by Fowler-Nordheim (F-N) tunneling.
However, when recording and deleting data, the related non-volatile semiconductor memory device temporarily removes electrons of a channel by controlling electrons in a transistor channel so as to turn on and off the transistor. For this, complicated processes for the tunnel oxide layer 11, the floating gate 12 and the ONO layer 14 are required. Also, high-quality materials are required to be durable under a high electric filed. Furthermore, since extremely high signals are necessary to store and delete the data, it becomes hard to drive the whole chip.